? semiconductor components industries, llc, 2006 june, 2006 ? rev. 6 1 publication order number: mc14543b/d mc14543b bcd?to?seven segment latch/decoder/driver for liquid crystals the mc14543b bcd?to?seven segment latch/decoder/driver is designed for use with liquid crystal readouts, and is constructed with complementary mos (cmos) enhancement mode devices. the circuit provides the functions of a 4?bit storage latch and an 8421 bcd?to?seven segment decoder and driver. the device has the capability to invert the logic levels of the output combination. the phase (ph), blanking (bi), and latch disable (ld) inputs are used to reverse the truth table phase, blank the display, and store a bcd code, respectively. for liquid crystal (lc) readouts, a square wave is applied to the ph input of the circuit and the electrically common backplane of the display. the outputs of the circuit are connected directly to the segments of the lc readout. for other types of readouts, such as light?emitting diode (led), incandescent, gas discharge, and fluorescent readouts, connection diagrams are given on this data sheet. applications include instrument (e.g., counter, dvm etc.) display driver, computer/calculator display driver, cockpit display driver, and various clock, watch, and timer uses. features ? latch storage of code ? blanking input ? readout blanking on all illegal input combinations ? direct led (common anode or cathode) driving capability ? supply voltage range = 3.0 v to 18 v ? capable of driving 2 low?power ttl loads, 1 lo w?power schottky ttl load or 2 htl loads over the rated temperature range ? pin?for?pin replacement for cd4056a (with pin 7 tied to v ss ). ? chip complexity: 207 fets or 52 equivalent gates ? pb?free packages are available* maximum ratings (voltages referenced to v ss ) parameter symbol value unit dc supply voltage range v dd ?0.5 to +18.0 v input voltage range, all inputs v in ?0.5 to v dd +0.5 v dc input current per pin i in 10 ma power dissipation per package (note 1) p d 500 mw operating temperature range t a ?55 to +125 c storage temperature range t stg ?65 to +150 c maximum continuous output drive current (source or sink) i ohmax i olmax 10 (per output) ma maximum continuous output power (source or sink) (note 2) p ohmax p olmax 70 (per output) mw stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above the recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may affect device reliability. 1. temperature derating: plastic ?p and d/dw? packages: ? 7.0 mw/ c from 65 c to 125 c 2. p ohmax = i oh (v oh ? v dd ) and p olmax = i ol (v ol ? v ss ) this device contains protection circuitry to guar d a gainst damage due to high static voltages or electr ic f ields. however, precautions must be taken to avo id a pplications of any voltage higher than maximum rate d v oltages to this high?impedance circuit. for prope r o peration, v in and v out should be constrained to th e r ange v ss (v in or v out ) v dd . unused inputs must always be tied to an appropria te l ogic voltage level (e.g., either v ss or v dd ). unuse d o utputs must be left open. http://onsemi.com see detailed ordering and shipping information in the package dimensions section on page 2 of this data sheet. ordering information *for additional information on our pb?free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. a = assembly location wl, l = wafer lot yy, y = year ww, w = work week g = pb?free package marking diagrams pdip?16 p suffix case 648 soic?16 d suffix case 751b 1 16 14543bg awlyww soeiaj?16 f suffix case 966 1 16 mc14543b alywg 16 1 mc14543bcp awlyywwg 1 1 1
mc14543b http://onsemi.com 2 truth table inputs outputs ld bi ph* d c b a a b c d e f g display x 1 0 x x x x 0 0 0 0 0 0 0 blank 1 0 0 0 0 001111110 0 1 0 0 0 0 010110000 1 1 0 0 0 0 101101101 2 1 0 0 0 0 111111001 3 1 0 0 0 1 000110011 4 1 0 0 0 1 011011011 5 1 0 0 0 1 101011111 6 1 0 0 0 1 111110000 7 1 0 0 1 0 001111111 8 1 0 0 1 0 011111011 9 1 0 0 1 0 1 0 0 0 0 0 0 0 0 blank 1 0 0 1 0 1 1 0 0 0 0 0 0 0 blank 1 0 0 1 1 0 0 0 0 0 0 0 0 0 blank 1 0 0 1 1 0 1 0 0 0 0 0 0 0 blank 1 0 0 1 1 1 0 0 0 0 0 0 0 0 blank 1 0 0 1 1 1 1 0 0 0 0 0 0 0 blank 000xxxx ** ** ? ? ? ? inverse of output display combinations as above above x = don?t care ? = above combinations * = for liquid crystal readouts, apply a square wave to ph for common cathode led readouts, select ph = 0 for common anode led readouts, select ph = 1 ** = depends upon the bcd code previously applied when ld = 1 pin assignment 13 14 15 16 9 10 11 12 5 4 3 2 1 8 7 6 d e g f v dd a b c d b c ld v ss bi ph a ordering information device package shipping ? mc14543bcp pdip?16 25 units / rail MC14543BCPG pdip?16 (pb?free) mc14543bd soic?16 48 units / rail mc14543bdg soic?16 (pb?free) mc14543bdr2 soic?16 2500 / tape & reel mc14543bdr2g soic?16 (pb?free) mc14543bf soeiaj?16 50 units / rail mc14543bfg soeiaj?16 (pb?free) ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d.
mc14543b http://onsemi.com 3 ????????????????????????????????? ????????????????????????????????? (voltages referenced to v ss ) characteristic symbo l v dd vdc ? 55 c 25 c 125 c unit min max min typ (note 3) max min max output voltage ?0? level v in = v dd or 0 v ol 5.0 10 15 ? ? ? 0.05 0.05 0.05 ? ? ? 0 0 0 0.05 0.05 0.05 ? ? ? 0.05 0.05 0.05 vdc ?1? level v in = 0 or v dd v oh 5.0 10 15 4.95 9.95 14.95 ? ? ? 4.95 9.95 14.95 5.0 10 15 ? ? ? 4.95 9.95 14.95 ? ? ? vdc input voltage ?0? level (v o = 4.5 or 0.5 vdc) (v o = 9.0 or 1.0 vdc) (v o = 13.5 or 1.5 vdc) v il 5.0 10 15 ? ? ? 1.5 3.0 4.0 ? ? ? 2.25 4.50 6.75 1.5 3.0 4.0 ? ? ? 1.5 3.0 4.0 vdc ?1? level (v o = 0.5 or 4.5 vdc) (v o = 1.0 or 9.0 vdc) (v o = 1.5 or 13.5 vdc) v ih 5.0 10 15 3.5 7.0 11 ? ? ? 3.5 7.0 11 2.75 5.50 8.25 ? ? ? 3.5 7.0 11 ? ? ? vdc output drive current (v oh = 2.5 vdc) source (v oh = 4.6 vdc) (v oh = 0.5 vdc) (v oh = 9.5 vdc) (v oh = 13.5 vdc) i oh 5.0 5.0 10 10 15 ? 3.0 ? 0.64 ? ? 1.6 ? 4.2 ? ? ? ? ? ? 2.4 ? 0.51 ? ? 1.3 ? 3.4 ? 4.2 ? 0.88 ? 10.1 ? 2.25 ? 8.8 ? ? ? ? ? ? 1.7 ? 0.36 ? ? 0.9 ? 2.4 ? ? ? ? madc (v ol = 0.4 vdc) sink (v ol = 0.5 vdc) (v ol = 9.5 vdc) (v ol = 1.5 vdc) i ol 5.0 10 10 15 0.64 1.6 ? 4.2 ? ? ? ? 0.51 1.3 ? 3.4 0.88 2.25 10.1 8.8 ? ? ? ? 0.36 0.9 ? 2.4 ? ? ? madc input current i in 15 ? 0.1 ? 0.00001 0.1 ? 1.0 adc input capacitance c in ? ? ? ? 5.0 7.5 ? ? pf quiescent current (per package) v in = 0 or v dd , i out = 0 a i dd 5.0 10 15 ? ? ? 5.0 10 20 ? ? ? 0.005 0.010 0.015 5.0 10 20 ? ? ? 150 300 600 adc total supply current (note 4, 5) (dynamic plus quiescent, per package) (c l = 50 pf on all outputs, all buffers switching) i t 5.0 10 15 i t = (1.6 a/khz) f + i dd i t = (3.1 a/khz) f + i dd i t = (4.7 a/khz) f + i dd adc 3. noise immunity specified for worst?case input combination. noise margin for both ?1? and ?0? level = 1.0 v min @ v dd = 5.0 v = 2.0 v min @ v dd = 10 v = 2.5 v min @ v dd = 15 v 4. to calculate total supply current at loads other than 50 pf: i t (c l ) = i t (50 pf) + 3.5 x 10 ?3 (c l ? 50) v dd f where: i t is in a (per package), c l in pf, v dd in v, and f in khz is input frequency. 5. the formulas given are for the typical characteristics only at 25 c.
mc14543b http://onsemi.com 4 ????????????????????????????????? ????????????????????????????????? (note 6) (c l = 50 pf, t a = 25 c) characteristic symbol v dd min typ max unit output rise time t tlh = (3.0 ns/pf) c l + 30 ns t tlh = (1.5 ns/pf) c l + 15 ns t tlh = (1.1 ns/pf) c l + 10 ns t tlh 5.0 10 15 ? ? ? 100 50 40 200 100 80 ns output fall time t thl = (1.5 ns/pf) c l + 25 ns t thl = (0.75 ns/pf) c l + 12.5 ns t thl = (0.55 ns/pf) c l + 12.5 ns t thl 5.0 10 15 ? ? ? 100 50 40 200 100 80 ns turn?off delay time t plh = (1.7 ns/pf) c l + 520 ns t plh = (0.66 ns/pf) c l + 217 ns t plh = (0.5 ns/pf) c l + 160 ns t plh 5.0 10 15 ? ? ? 605 250 185 1210 500 370 ns turn?on delay time t phl = (1.7 ns/pf) c l + 420 ns t phl = (0.66 ns/pf) c l + 172 ns t phl = (0.5 ns/pf) c l + 130 ns t phl 5.0 10 15 ? ? ? 505 205 155 1650 660 495 ns setup time t su 5.0 10 15 350 450 500 ? ? ? ns hold time t h 5.0 10 15 40 30 20 ? ? ? ns latch disable pulse width (strobing data) t wh 5.0 10 15 250 100 80 125 50 40 ? ? ? ns 6. the formulas given are for the typical characteristics only. logic diagram v dd = pin 16 v ss = pin 8 b3 ld1 d4 c2 a5 phase6 14g 15f 13e 12d 11c 10b 9a bi7
mc14543b http://onsemi.com 5 figure 1. typical output source characteristics figure 2. typical output sink characteristics ?24 ?18 ?12 ?6.0 0 i oh , source current (madc) (v oh ? v dd ), source device voltage (vdc) ?16 ?12 ?8.0 ?4.0 0 v dd = 5.0 vdc p ohmax = 70 mwdc v dd = 10 vdc v dd = 15 vdc v ss = 0 vdc 0 6.0 12 18 24 i ol , sink current (madc) (v ol ? v ss ), sink device voltage (vdc) 0 4.0 8.0 12 16 v dd = 15 vdc v dd = 10 vdc v dd = 5.0 vdc v ss = 0 vdc p olmax = 70 mwdc figure 3. dynamic power dissipation signal waveforms inputs bi and ph low, and inputs d and ld high. f in respect to a system clock. figure 4. dynamic signal waveforms (a) inputs d, ph, and bi low, and inputs a, b, and ld high. (b) inputs d, ph, and bi low, and inputs a and b high. (c) data dcba strobed into latches 20 ns 20 ns v dd v ss v oh v ol 10% 50% 90% 1 2f 50% duty cycle a, b, and c any output all outputs connected to respective c l loads. 20 ns 20 ns 90% 10% 50% t phl t plh 90% 50% 10% v dd v ss v oh v ol v dd v ss v dd v ss v oh v ol v dd v ss t thl t tlh c g ld c g ld 20 ns 90% 50% 10% 50% 50% t h t su 50% t wh
mc14543b http://onsemi.com 6 connections to various display readouts liquid crystal (lc) readout light emitting diode (led) readout incandescent readout note: bipolar transistors may be added for gain (for v dd 10 v or i out 10 ma). gas discharge readout connections to segments square wave (v ss to v dd ) common backplane one of seven segments mc14543b output ph mc14543b output ph v ss appropriate voltage mc14543b output ph v ss common cathode led common anode led v dd mc14543b output ph v dd mc14543b output ph appropriate voltage v ss v dd = pin 16 v ss = pin 8 0123456789 display a b c d e fg
mc14543b http://onsemi.com 7 package dimensions notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: inch. 3. dimension l to center of leads when formed parallel. 4. dimension b does not include mold flash. 5. rounded corners optional. ?a? b f c s h g d j l m 16 pl seating 18 9 16 k plane ?t? m a m 0.25 (0.010) t dim min max min max millimeters inches a 0.740 0.770 18.80 19.55 b 0.250 0.270 6.35 6.85 c 0.145 0.175 3.69 4.44 d 0.015 0.021 0.39 0.53 f 0.040 0.70 1.02 1.77 g 0.100 bsc 2.54 bsc h 0.050 bsc 1.27 bsc j 0.008 0.015 0.21 0.38 k 0.110 0.130 2.80 3.30 l 0.295 0.305 7.50 7.74 m 0 10 0 10 s 0.020 0.040 0.51 1.01 pdip?16 case 648?08 issue t soic?16 case 751b?05 issue j notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimensions a and b do not include mold protrusion. 4. maximum mold protrusion 0.15 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.127 (0.005) total in excess of the d dimension at maximum material condition. 18 16 9 seating plane f j m r x 45 g 8 pl p ?b? ?a? m 0.25 (0.010) b s ?t? d k c 16 pl s b m 0.25 (0.010) a s t dim min max min max inches millimeters a 9.80 10.00 0.386 0.393 b 3.80 4.00 0.150 0.157 c 1.35 1.75 0.054 0.068 d 0.35 0.49 0.014 0.019 f 0.40 1.25 0.016 0.049 g 1.27 bsc 0.050 bsc j 0.19 0.25 0.008 0.009 k 0.10 0.25 0.004 0.009 m 0 7 0 7 p 5.80 6.20 0.229 0.244 r 0.25 0.50 0.010 0.019
mc14543b http://onsemi.com 8 package dimensions soeiaj?16 case 966?01 issue a h e a 1 dim min max min max inches ??? 2.05 ??? 0.081 millimeters 0.05 0.20 0.002 0.008 0.35 0.50 0.014 0.020 0.10 0.20 0.007 0.011 9.90 10.50 0.390 0.413 5.10 5.45 0.201 0.215 1.27 bsc 0.050 bsc 7.40 8.20 0.291 0.323 0.50 0.85 0.020 0.033 1.10 1.50 0.043 0.059 0 0.70 0.90 0.028 0.035 ??? 0.78 ??? 0.031 a 1 h e q 1 l e 10 0 10 l e q 1 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimensions d and e do not include mold flash or protrusions and are measured at the parting line. mold flash or protrusions shall not exceed 0.15 (0.006) per side. 4. terminal numbers are shown for reference only. 5. the lead width dimension (b) does not include dambar protrusion. allowable dambar protrusion shall be 0.08 (0.003) total in excess of the lead width dimension at maximum material condition. dambar cannot be located on the lower radius or the foot. minimum space between protrusions and adjacent lead to be 0.46 ( 0.018). m l detail p view p c a b e m 0.13 (0.005) 0.10 (0.004) 1 16 9 8 d z e a b c d e e l m z on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its of ficers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800?282?9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81?3?5773?3850 mc14543b/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303?675?2175 or 800?344?3860 toll free usa/canada fax : 303?675?2176 or 800?344?3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative
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